This invention pertains to high power, high voltage devices with increased stability of breakdown voltage at increased temperatures and increased reverse bias (HTRB test), and more particularly to high voltage termination structures in silicon power devices.
It is known to persons familiar with the art that high voltage terminations in power devices are unstable under high voltage high temperature stresses (HTRB) due the changes in the distribution of charge in silicon, changes induced by the movement or the injection of the charge in the oxide overlaying the silicon in the termination region.
Most, if not all, high voltage termination in silicon power devices consist of layers of opposite polarity (e.g. P-layers if the starting material is N-doped Silicon) covered by oxide, in most, if not all, cases thermally grown. The overlaying oxide has to have low mobile charge and low interface traps, susceptible to become “charged” under the high electric field conditions which are normal when the semiconductor device is under high voltage reverse bias conditions, especially if the ambient temperature is also high.
A few not limiting examples of high voltage termination are: annular P-type rings; P rings with field plates (floating or connected to the P-rings); continuous P-ring with spiral layout; RESURF termination; and variable lateral doping (VLD) termination or junction termination extension. In all cases, bi-dimensional simulations indicate multiple high electric field points in the structure. An illustration of such a TCAD bi-dimensional simulation is shown in FIG. 1A for a power device of the type illustrated in FIG. 1B. FIG. 1A shows electric field distribution across a P-ring termination with floating field plates. High peaks of electric field are visible in the silicon substrate and at the Si—SiO2 interface. Such high electric points in the structure are prone to generate hot carriers, hot electrons and hot holes, that can reach energy levels high enough to jump into the oxide as illustrated in FIGS. 1C and 1D. Once trapped in the oxide, the hot carriers (hot holes in particular) can deplete the P-type regions underneath the oxide or can accumulate in the N-type doping and the surface, in both cases degrading the blocking capability of the device. Such trapping and degradation also appears in the case of junction termination extension as shown in FIGS. 1E and 1F.
More so, charge of either sign (positive or negative) can diffuse through the passivation layer into the field oxide (the oxide grown or deposited in the termination area) and can pile up at the boundaries of the P diffused rings. The presence of the charge in the oxide (either “injected” from the silicon due to the high concentration of hot carriers or diffused through the oxide due to harsh environment conditions) alters the distribution of doping in silicon and creates conditions for an even higher electric field, therefore degrading the blocking voltage of the device. Similar problems can occur with N diffused rings in a P-type substrate.
An example of an attempted solution to this problem is described by D. Jaume et al., High-Voltage Planar Devices Using Field Plate and Semi-Resistive Layers, IEEE Transactions on Electron Devices, Vol. 38, No. 7, July 1991, pp. 1681-84. Their solution involves depositing a semi-insulating polycrystalline silicon (SIPOS) layer over the 1.25 micron thick oxide layer overlaying the silicon substrate. A similar approach is described in C. B. Goud, Two Dimensional Analysis and Design Considerations of High Voltage Planar Junctions Equipped with Field Plate and Guard Ring, IEEE Transactions on Electron Devices, Vol. 38, No. 6, June 1991, pp. 1497-1504. This approach omits the SIPOS layer but show results for oxide layers ranging from about 1.5 micron to over 8 microns thickness.
The approach of using a thick oxide layer overlaying the silicon substrate continues to be used, as shown, for example in Schulze et al. U.S. Pat. No. 7,541,660, (Jun. 2, 2009), together with laterally varying dopant density in the field limiting rings. The foregoing arrangements reduce field effects but do not eliminate charge trapping problems.
Another approach applicable to wide-band gap power devices, described in Van Zeghbroeck U.S. Pat. No. 7,498,651, interconnects the rings of the termination structure formed on top of a SiC substrate around an active area by means of resistive shorting bars. Such devices do not face the same problem as in silicon devices wherein the termination structure is implanted or diffused into the substrate because the substrate is more highly doped.
A much older approach is described in the textbook by A. Blicher, Field-Effect and Bipolar Power Transistor Physics (1981) at pp. 60 and 227-229, citing L. E. Clark and D. S. Zoroglu, Enhancement of Breakdown Properties of Overlay Annular Diodes by Field Shaping Resistive Films, Solid State Electronics, 15: 653-657, 1972. In this article, the authors compare using a layer of thick oxide (7 microns) on the silicon surface with a layer of undoped polysilicon film of 200 nm thickness over a 2 micron layer of oxide on the silicon surface. Blicher then states at page 61 that a considerably improved version of the simple polycrystalline film is the semi-insulating polycrystalline silicon (Sipos) described in the next section of the text. In that section and again at page 230, the author cites (at Page 230) Aoki et al, Oxygen-doped Polycrystalline Silicon Films Applied to Surface Passivation, J. Electrochem. Soc. Technical Digest, March 1975, pp. 167-170, and Matsushita et al, Highly Reliable High Voltage Transistors by Use of the SIPOS Process, IEDM Technical Digest, Washington, December 1975, 167-170 as using an oxygen-doped polycrystalline (Sipos) film in place of the silicon dioxide layer, and then applying silicon nitride and oxide films. In footnote 1 on page 228, the author states that Aoki et al used direct deposition on silicon of polycrystalline silicon containing 10-25 weight percent oxygen and found it superior to the directly deposited, undoped polycrystalline films from a surface stability and leakage point of view. Matsushita et al (coauthor with Aoki) used a triple layer structure including a 5000  thick oxygen-doped polycrystalline silicon. The use of variations of the Sipos structure has been established as the usual passivation approach in the field, and use of undoped polycrystalline silicon has not been favored.
Because of discontinuities and stacking faults at the interface between the underlying silicon epi or substrate surface and the deposited polysilicon layer, however, the Sipos structure causes increased leakage current. According to Blicher, Matsushita et al. report that the leakage current in the Sipos film can be as small as if passivated by silicon dioxide if the oxygen concentration in the polysilicon is sufficiently high. But if, as Blicher explains at page 61, the Sipos film is made too resistive by excessive oxygen doping, then the breakdown approaches that of thermal oxide. This approach thus presents tradeoffs between leakage current and breakdown characteristics.
Accordingly, a need remains for a better way to form an edge termination structure in silicon power devices with high voltage blocking capability and with a stable blocking voltage under the most adverse conditions by eliminating the conditions of charge injection in an oxide overlaying the edge termination while controlling leakage current.